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[00:03:22] <KimK> Wait, I thought the last outfit wasn't interested enough to even lend you their I/O card. Now someone is offering to pay you?
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[00:05:43] <andypugh> Wierd world, isn't it?
[00:06:03] <andypugh> I refused. I'd rather work for free.
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[00:07:18] <KimK> Ha!
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[00:09:13] <andypugh> If you are working for free, then failure _is_ an option.
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[00:20:43] <andypugh> Hostmot2 stepgen has grown a bunch of debug pins. I had never seen them before, are that meant to be there?
[00:22:01] <KimK> Sorry, I don't know. I'll bet Seb would, though.
[00:22:54] <andypugh> It looks like somebody is doing a bunch of work to gat velocity mode working, perhaps for step/dir servo drives?
[00:23:30] <andypugh> Or maybe it has always been there, and i didn't notice?
[00:24:36] <KimK> Seb's the guy to ask.
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[00:33:03] <pcw_home> AFAIK velocity mode works fine, There are some problems with the HM2 stepgen in high jitter environments that need to be fixed
[00:33:05] <pcw_home> that is it could be a lot more tolerant of host jitter than it is
[00:35:02] <andypugh> The debug pins might always have been there, but they are not in the docs.
[00:35:42] <andypugh> GTAG 9 and GTAG 10 Are?
[00:36:20] <andypugh> I have nver quite figured out how to identify gtags, they don;t seem to be in the pin file, or the regmap
[00:37:57] <pcw_home> UARTTX and UARTRX
[00:38:29] <pcw_home> The are only in the VHDL source I think (IDROMCosnt.vhd)
[00:38:53] <pcw_home> IDROMConst.vhd
[00:39:11] <andypugh> So, you can have a firmware with just TX or just RX?
[00:40:10] <pcw_home> They _should_ be in the regmap
[00:40:11] <pcw_home> Well they are independent (except UARTRX RXMASK comes from UARTTX)
[00:41:10] <andypugh> Just wondering if there will ever be different numbers of them, or whether a driver can assume pairs.
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[00:43:23] <pcw_home> Actually not sure, I think they depend entirely on the pinout, if you only have a UARTRX0 pin you will only get a UARTRX
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[00:44:45] <andypugh> Hmm, so a UART Hm2 module needs to keep independent lists of TX and TX functions.
[00:45:34] <pcw_home> I can't quite imagine much use for an unpaired RX or TX so I wouldn't make such a config
[00:45:36] <pcw_home> so you could defer such support till its really needed (probably never)
[00:45:49] <andypugh> Isssy is wanting it
[00:45:58] <andypugh> Ah, well, not that bit
[00:46:29] <andypugh> OK, so I will assume pairs for the time being.
[00:48:23] <pcw_home> They are totally independent for flexibility (but for example in SSLBP in the internal UARTs we overlap the RX/TX data registers and baud rate registers)
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[00:50:28] <pcw_home> The HM2 UARTs are "funny" in that they have 32 bit host interface (with push 1,2,3,4 byte and pop 1,2,3,4 bytes access addresses)
[00:51:03] <andypugh> Yeah, I spotted that part. Not unlike the BSPI
[00:52:08] <andypugh> loadrt hm2_pci config="num_uarts=104412" is probably how that will be handled.
[00:52:45] <pcw_home> umm thats a lot of UARTs
[00:53:18] <andypugh> It's 6, with 1, zero, 4 byte access..
[00:56:19] <pcw_home> Wouldn't it just be" num_uarts=6"
[00:56:21] <pcw_home> the push/pop size is just determined by what needed to send/whats in the FIFO
[00:56:25] <andypugh> Is writing one word per thread OK do you think? It's a lot easier to just have a u32 HAL pin to put the data on than to figure out a way to send multiple words per thread
[00:57:04] <andypugh> The hm2 driver needs to know the read/write address to use at load time.
[01:00:01] <andypugh> The first thing that a generic Hm2 driver does is set up TRAM reads and writes to/from specific registers.
[01:02:59] <pcw_home> yeah Its pretty awkward with unknown packet sizes if you want not to have to read/write a byte at a time
[01:03:01] <pcw_home> Probably for EMCs HM2 driver a different interface would be better (maybe a 32 bit FIFO and a byte count/ send packet register)
[01:03:46] <andypugh> HAL isn't good at FIFOs
[01:04:21] <andypugh> And looking at Isssy's protocol, he wants to send 5 bytes
[01:04:56] <pcw_home> Let me think about this and see If I can come up with a better interface
[01:05:54] <pcw_home> (actually SSERIAL with isssy firmware would be better)
[01:05:55] <andypugh> I would have told him to use the raw interface, but that only toggles in one word per thread.
[01:07:03] <andypugh> SPI would be easier still, I have written an interface to let comp modules write to the SPI buffer.
[01:08:02] <pcw_home> maybe theres some simple generic SSERIAL code for small packet apps
[01:08:03] <pcw_home> (packet send/recv size in CSR data in mailboxes, doit command for transfer)
[01:08:33] <pcw_home> good for up to 12 byes in/out
[01:09:18] <pcw_home> I presume he wants one packet/thread
[01:10:29] <andypugh> I was hoping to write a generic HAL driver, not an Issy-specific module.
[01:11:11] <pcw_home> We have the same data issues with the 7I73 pendant interface: the keypad data and LCD data are streams
[01:11:35] <andypugh> The answer might be a run a base thread to read/write the FIFOs
[01:13:02] <pcw_home> The other way is limit your driver to fixed packet sizes and then figure out the addresses based on the packet size
[01:15:30] <andypugh> I was wondering about just using 32 byte writes, and then letting them choose how many words they want to send. then the HAL interface could be (for example) 6 separate u32 HAL pins per UART, for6 slots in the FIFO
[01:16:55] <pcw_home> Well Let me think about this a bit I do think theres a better UART interface possible for EMCs HM2 driver use
[01:17:21] <andypugh> We have one user. It is debatable how much effort is it worth.
[01:18:39] <pcw_home> I think sserial is better if its a synchronous packet interface
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[01:19:29] <pcw_home> I mean sserial_isssy ( not sserisl_sslbp)
[01:19:57] <andypugh> How about, config="conf_uart=122143:11111" which would be 2 active UARTS, one which fills 6 FIFO slots per cycle, with 1 or 2 r 4 or 3 bytes, and the other which fills 5 one-byte slots.
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[01:20:49] <pcw_home> ewww
[01:20:51] <andypugh> hal pins like ...uart.0.fifo-00, uart.0.fifo-01
[01:22:16] <pcw_home> I like num_uarts=6, txpktsize=5, rxpktsize=7
[01:22:33] <andypugh> The problem is the HAL paradigm, which is that pins are read and acted on once per thread, and the hm2 paradigm that the register a value goes to is always the same one.
[01:23:37] <andypugh> pcw_home: And assume that all uarts have the same config?
[01:23:44] <pcw_home> Yeah and it gets worse with DMA (where you can avoid doing writes) so all operations need to be data dependent
[01:24:06] <pcw_home> you _cant_ avoid
[01:24:28] <andypugh> DMA (well, TRAM) is the reason for much of this trouble.
[01:25:03] <pcw_home> how about the UART changes to 1,2,3 bytes per write with the number specified in the MSB of the 32 bit word
[01:25:25] <pcw_home> oops thats no good fore reads
[01:25:38] <andypugh> Or for 4-byte writes
[01:26:16] <pcw_home> No its OK, the MSB readdata tells you how many valid bytes you got
[01:27:18] <pcw_home> (well of course you would lose 4 byte read/writes but now only a single address is needed and we are still up to 3x lower I/O 0verhead than a 8 bit uart)
[01:29:35] <andypugh> I need to talk to Issy, he has a 5-byte protocol so possibly can't use uarts at all. He probably needs to send/receive DIO as 2 x (tag + 2 bytes) rather than 1 x (tag + 4 bytes)
[01:30:09] <andypugh> Unless his protocol is actually 14 single bytes.
[01:30:22] <pcw_home> Like I said let me give it some thought I think theres probably a better way...
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[01:36:32] <pcw_home> The UARTS are really for streams but I expect isssy wants a packet interface
[01:36:34] <pcw_home> So a "packet UART" migh be better this would avoid the multiple address issue of the current
[01:36:36] <pcw_home> stream oriented UARTS
[01:37:08] <andypugh> I am composing an email to him, I will CC you.
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[16:13:17] <CIA-11> EMC: 03jepler 07master * rf276ca163a95 10/src/rtapi/rtai_rtapi.c: Don't use linux API for delays
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[17:05:25] <CIA-11> EMC: 03mshaver 07master * r21684923df80 10/src/hal/drivers/mesa-hostmot2/sserial.c: Revert previous commit to allow Andy Pugh's patch to apply cleanly
[17:05:27] <CIA-11> EMC: 03mshaver 07master * ref70d18d7ad1 10/src/rtapi/rtai_rtapi.c: Merge branch 'master' of ssh://git.linuxcnc.org/git/emc2
[17:08:03] <CIA-11> EMC: 03mshaver 07v2.5_branch * r88ef30e0bb62 10/src/hal/drivers/mesa-hostmot2/sserial.c: Revert previous commit to allow Andy Pugh's patch to apply cleanly
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[19:25:51] <Guest986> is there encoder support in pluto-p stepper version now????
[19:28:48] <andypugh> I can't see it in the manual
[19:29:15] <andypugh> Do you already have the Pluto?
[19:30:23] <andypugh> There is something only slightly more expensive which actually works, and which definitely can mix steppers and encoders.
[19:33:05] <Guest986> its not in manual .. if you are talking about mesa than i know it... right now i am working on a projet to port EMC2 on MiniARM2440
[19:34:24] <Guest986> RTAI + MiniARM failes.. but Xenomai is working perfectly fine on this board.. latency is higher than i expected.. but i cann reduce it...
[19:35:09] <Guest986> EMC not working with Xenomai not even with RTskin..:(
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[20:02:24] <andypugh> So where does the Pluto fit into this?
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[20:36:15] <Guest986> software stepgen wont work.so i want to use system bus to connect to FPGA
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